The present invention relates to microelectronic devices and fabrication methods therefor, more particularly, to interconnects for microelectronic devices and fabrication methods therefor.
As the integration level of microelectronic devices increases, interconnects for these devices, which can significantly influence the speed, product yield, and reliability of the device, increasingly employ a multi-layered structure. Conventional techniques for forming such a multilevel interconnect typically employ a planarization process to increase resolution and depth-of-focus in photolithography. In particular, a planarization process using spun-on-glass (SOG) has been widely applied because of advantages of low cost, process simplification, no need for a poisonous gas, and tendency to form a low defect density when compared with other planarization processes.
In a typical planarization process using SOG, liquid SOG is coated on a semiconductor substrate to form an SOG layer, which is then baked in a range of 150-400xc2x0 C. to remove solvents and moisture. During this process, the SOG is condensed and tensile stresses may develop in the SOG layer, producing fine cracks in the SOG layer, especially in SOG layers having thicknesses of 3,000 xc3x85 or more.
The SOG layer tends to form more thickly in areas adjacent to the edge of a semiconductor wafer. As thin films are continuously deposited, very large steps, that is, steps of 2.0 xcexcm or more, may be formed between the edge of a semiconductor wafer and adjacent areas for forming devices thereon, as the edge of the semiconductor wafer typically is not exposed in photolithography. Consequently, an SOG layer formed in this area may have a thickness of 2.0 xcexcm or more, and thus may be more susceptible to cracks.
To reduce formation of such fine cracks, an organic SOG containing an organic group such as a methyl (CH3xe2x88x92) group or a phenyl (C6H5xe2x88x92) group is usually used instead of an inorganic SOG which lacks such a group. However, organic SOG typically is more volatile and harder to contain than inorganic SOG.
FIGS. 1-3 are cross-sectional views showing a conventional method for forming a multilevel interconnects in a semiconductor device. Referring to FIG. 1, a conductive pattern 30 is formed on a semiconductor substrate 10 having a first insulation layer 20 formed thereon. A second insulation layer 40 is then formed to a uniform thickness on the overall surface of the resultant structure, covering the conductive pattern 30. Steps are typically formed in the second insulation layer pattern 40 due to the presence of the conductive pattern 30. A first area H is defined where the height between the surface of the semiconductor substrate 10 and the surface of the second insulation layer 40 is relatively high, and a second area L is defined where the height is relatively low.
Subsequently, lower conductive patterns 50a, 50b, and 50c are formed on the second insulation layer 40. Here, the first lower conductive pattern 50a is formed in the first area H, and the second and third lower conductive patterns 50b and 50c are formed in the second area L. The second lower conductive pattern 50b is positioned between the first and third lower conductive patterns 50a and 50c. 
A third insulation layer 60 is formed, covering lower conductive patterns 50a, 50b, and 50c. An SOG layer 70 is then formed by coating an inorganic or organic SOG on the third insulation layer 60 using a spin-on process. Here, SOG typically flows into the second area L due to its high fluidity, making the SOG layer thicker in the second area L than in the first area H. Therefore, the SOG layer 70 tends to be relatively planar, and is thickest in a portion A of the area L adjacent to the first area H.
The SOG layer 70 is then baked at between 150 and 400xc2x0 C. to remove solvents and moisture from the SOG layer 70. During this baking process, the thicker portion A of the SOG layer 70 tends to be more susceptible to fine cracks. Though fine cracks can be reduced by forming the SOG layer 70 of an organic SOG instead of an inorganic SOG, it is difficult to efficiently reduce the stress-induced fine cracks due to the thickness of the portion A of the SOG layer 70.
Referring to FIG. 2, a planarization layer 70a is formed by uniformly etching back the overall surface of the SOG layer 70 to a predetermined depth until the third insulation layer 60 on the third lower conductive pattern 50c is exposed. The reason for etch-back is to further planarize the surface of the SOG layer 70 and reduce the aspect ratio of a later-formed via hole.
Because the SOG layer 70 is thinner on the first lower conductive pattern 50a than on the third lower conductive pattern 50c, the third insulation layer 60 on the first lower conductive pattern 50a is typically exposed. However, because the SOG layer 70 is thicker on the second lower conductive pattern 50b than on the third conductive pattern 50c, the third insulation layer 60 on the second lower conductive pattern 50b typically is not exposed.
A fourth insulation layer 80 is then formed on the surface of the resultant structure. A photoresist layer pattern 90a is formed on the fourth insulation layer 80 to expose the fourth insulation layer 80 on the second and third lower conductive patterns 50b and 50c. Referring to FIG. 3, a fourth insulation layer pattern 80a having via holes for exposing the second and third lower conductive patterns 50b and 50c, respectively, a planarization layer pattern 70b, and a third insulation layer pattern 60a are formed by sequentially etching the fourth insulation layer 80, the planarization layer 70a, and the third insulation layer 60, using the photosensitive layer pattern 90a as an etching mask.
To simultaneously expose the second and third lower conductive patterns 50b and 50c, the upper portion of the second lower conductive pattern 50b typically is further etched. When etching is performed for the purpose of exposing the third lower conductive pattern 50c, the second lower conductive pattern 50b may not be exposed. On the other hand, when etching is performed for the purpose of exposing the second lower conductive pattern 50b, the upper portion of the third conductive pattern 50c may be over-etched, and the via hole for exposing the third lower conductive pattern 50c may become wider, potentially resulting in formation of a connection between the via hole and an adjacent via hole (not shown), or exposing another conductive layer which should not be exposed.
First and second upper conductive patterns 100a and 100b are then formed on the fourth insulation layer pattern 80a to make contact with the second and third lower conductive patterns 50b and 50c through the via holes, respectively.
If the SOG layer 70 is formed of an organic SOG to reduce fine cracks on the planarization layer 70a in area A, high molecular weight substances may be produced during forming the via hole for exposing the second lower conductive pattern 50b. These high molecular weight substances may locally accumulate on the second lower conductive pattern 50b, thereby increasing contact resistance. High molecular weight substances typically are formed because silicon (Si) and oxygen (O) components of the organic SOG are vaporized as silicon fluoride (SiF4) and carbon dioxide (CO2) during etching by a carbon fluoride (CF4 or C2F6) etching gas, whereas organic components of the organic SOG are not removed.
According to the conventional method described above, the SOG planarization layer 70a in area A is susceptible to fine cracks. The second lower conductive pattern 50b may not make contact with the first upper conductive pattern 100a. In addition, the via hole exposing the third lower conductive pattern 50c may be larger than intended.
In light of the foregoing, it is an object of the present invention to provide interconnects for microelectronic devices and methods of fabrication therefor which have planarized spun-on-glass (SOG) regions which are less susceptible to formation of fine cracks and which are less likely to produce deformed via holes for interconnecting regions formed thereon.
These and other objects, features and advantages are provided according to the present invention by interconnects and methods of fabrication therefor in which a conductive mesa upon which an interconnect is to be formed is formed a sufficient distance from an adjacent mesa such that an overlying spun-on glass (SOG) planarization layer formed thereon is substantially removed from the interconnect mesa upon planarization of the SOG layer to form a planarized SOG region. Consequently, when an overlying insulation layer is formed on the interconnect mesa, via holes formed therethrough are less likely to be distorted. In addition, because of the separation between the mesas, the SOG layer tends to be thinner, thus helping reduce the formation of fine cracks therein.
In particular, according to the present invention, an interconnect in a microelectronic device is formed by forming a first mesa on a substrate. A first insulation layer is then formed on the substrate, the first insulation layer covering the first mesa to define a step at an edge thereof. A second mesa is formed on the first insulation layer adjacent the step, the second mesa being lower than the step. A second insulation layer is formed on the substrate, covering the second mesa and forming a step in the second insulation layer overlying the step in the first insulation layer. A spun-on-glass (SOG) layer is then formed on the second insulation layer, and then is planarized to expose a first portion of the second insulation layer at the step in the second insulation layer and to expose a second portion of the second insulation layer overlying the second mesa, thereby defining a planarized SOG region between the step and the second mesa. A third insulation layer is formed on the substrate, covering the planarized SOG region, and portions of the second and third insulation layers overlying the second mesa are then removed to expose a portion of the second mesa. An interconnecting region is formed on the second insulation layer which extends through the second and third insulation layers to contact the exposed portion of the second mesa.
According to a first embodiment of the present invention, a first conductive mesa is formed on a substrate, the first conductive mesa having a first thickness. A first insulation layer is then formed on the substrate, the first insulation layer covering the first conductive mesa to define a step at an edge thereof. A second conductive mesa is formed on the first insulation layer adjacent the step, the second conductive mesa being laterally disposed a distance from the first conductive mesa at least three (3) times greater than the first thickness and having a second thickness less than the first thickness. A second insulation layer is formed on the substrate, covering the second conductive mesa and forming a step in the second insulation layer overlying the step in the first insulation layer. A spun-on-glass (SOG) layer is formed on the second insulation layer and planarized to expose a first portion of the second insulation layer at the step in the second insulation layer and to expose a second portion of the second insulation layer overlying the second conductive mesa, thereby defining a planarized SOG region between the step and the second conductive mesa. A third insulation layer is formed on the substrate, covering the planarized SOG region, and portions of the second and third insulation layers overlying the second conductive mesa are removed to expose a portion of the second conductive mesa. A conductive interconnecting region is formed on the second insulation layer which extends through the second and third insulation layers to contact the exposed portion of the second conductive mesa. Preferably, the first thickness is in a range from 5000 xc3x85 to 10,000 xc3x85, and the second thickness is less than two-thirds (⅔) of the first thickness.
According to a second embodiment of the present invention, a first conductive mesa is formed on a substrate, the first conductive mesa having a first thickness. A first insulation layer is formed on the substrate, the first insulation layer covering the first conductive mesa to form a step at an edge thereof. A conductive layer and a second conductive mesa having a second thickness less than the first thickness are then formed on the first insulation layer. The second conductive mesa is laterally disposed a distance from the first conductive mesa at least three (3) times greater than the first thickness. The conductive layer overlies the first mesa and extends over the step in the first insulation layer towards the second conductive mesa, and has an edge disposed past the first mesa towards the second conductive mesa a distance at least three (3) times greater than the first thickness. A second insulation layer is then formed covering the second conductive mesa and the conductive layer to form first a first step in the second insulation layer overlying the step in the first insulation layer and a second step in the second insulation layer overlying the edge of the conductive layer, the second step being nearer the second conductive mesa than the first step. A spun-on-glass (SOG) layer is formed on the second insulation layer, and then is planarized to expose respective portions of the second insulation layer at respective ones of the first and second steps in the second insulation layer and to expose a portion of the second insulation layer overlying the second conductive mesa, thereby forming a first planarized SOG region disposed between the second conductive mesa and second step in the second insulation layer and a second planarized SOG region disposed between the first and second steps in the second insulation layer. A third insulation layer is formed covering the first and second planarized SOG regions, and portions of the second and third insulation layers overlying the second conductive mesa are removed to expose a portion of the second conductive mesa. A conductive interconnecting region is formed on the second insulation layer which extends through the second and third insulation layers to contact the exposed portion of the second conductive mesa. Preferably, the first thickness is in a range from 5,000 xc3x85 to 10,000 xc3x85, and the second thickness is less than two-thirds (⅔) of the first thickness.
According to a third embodiment of the present invention, a first conductive mesa is formed on a substrate, the first conductive mesa having a first thickness. A first insulation layer is then formed on the substrate, the first insulation layer covering the first conductive mesa to form a step at an edge thereof A conductive layer and a second conductive mesa having a second thickness less than the first thickness are then formed on the first insulation layer. The second conductive mesa is laterally disposed a distance from the first conductive mesa a distance which is at least three (3) times greater than the first thickness. The conductive layer is disposed on the first mesa and has an edge disposed towards the second conductive mesa. A second insulation layer is formed covering the second conductive mesa and covering the conductive layer to form a first step in the second insulation layer overlying the edge of the conductive layer and a second step in the second insulation layer overlying the step in the first insulation layer, the second step being nearer the second conductive mesa than the first step. A spun-on-glass (SOG) layer is formed on the second insulation layer, and then is planarized to expose respective portions of the second insulation layer at respective ones of the first and second steps in the second insulation layer and to expose a portion of the second insulation layer overlying the second conductive mesa, thereby forming a first planarized SOG region disposed between the second conductive mesa and second step in the second insulation layer and a second planarized SOG region disposed between the first and second steps in the second insulation layer. A third insulation layer is formed covering the first and second planarized SOG regions, and portions of the second and third insulation layers overlying the second conductive mesa are removed to expose a portion of the second conductive mesa. A conductive interconnecting region is formed on the second insulation layer which extends through the second and third insulation layers to contact the exposed portion of the second conductive mesa. Preferably, the first thickness is in a range from 5,000 xc3x85 to 10,000 xc3x85 and the second thickness is less than two-thirds (⅔) of the first thickness.
According to a fourth embodiment of the present invention, a dummy mesa is formed on a substrate, and a first insulation layer is formed covering the dummy mesa. A first conductive mesa is formed on the first insulation layer on a first side of the dummy mesa, the first conductive mesa having a first thickness greater than the dummy mesa. A second insulation layer is formed on the substrate, the second insulation layer covering the first conductive mesa to form a step at an edge thereof. A second conductive mesa is formed on the second insulation layer on a side of the dummy mesa opposite of the first conductive mesa and a third conductive mesa is formed on the second insulation layer overlying the first conductive mesa, the second and third conductive mesas having a second thickness less than the first thickness. A third insulation layer is then formed on the substrate, covering the step in the second insulation layer and the second conductive mesa and forming a step in the third insulation layer overlying the step in the second insulation layer. A spun-on-glass (SOG) layer is formed on the third insulation layer, and then is planarized to expose a first portion of the third insulation layer at the step in the third insulation layer and to expose a second portion of the third insulation layer overlying the second conductive mesa, thereby defining a planarized SOG region between the step in the third insulation layer and the second conductive mesa. A fourth insulation layer is formed on the substrate, covering the planarized SOG region, and portions of the third and fourth insulation layers overlying the second conductive mesa are removed to expose a portion of the second conductive mesa. A conductive interconnecting region is formed on the fourth insulation layer that extends through the third and fourth insulation layers to contact the exposed portion of the second conductive mesa. Preferably, the first thickness is in a range from 5000 xc3x85 to 10,000 xc3x85, and the second thickness is less than two-thirds (⅔) of the first thickness.
Microelectronic devices formed by the above-described techniques are also discussed.